1. Field of the Invention
The present invention relates to decoder circuits, and particularly those suitable for programmable memory arrays, and more particularly those suitable for semiconductor integrated circuit memory arrays incorporating passive element memory cells.
2. Description of the Related Art
Certain passive element memory cells exhibit re-writable characteristics. For example, in certain memory cells programming may be achieved by forwarding biasing the memory cell (e.g., with reference to the polarity of a diode therewithin) with a voltage of approximately 6-8V, while erase may be achieved by reverse biasing the memory cell with a voltage of approximately 10-14V. These high voltages require use of special high voltage CMOS transistors within the word line and bit line decoders. These high-voltage transistors do not scale well as the memory cell word line pitch and bit line pitch decrease. This is particularly problematic for 3D memory technology, in which the sheer density of word lines and bit lines exiting the array, and which must be interfaced with a word line and bit line driver, makes even more important the ability to provide decoder circuits compatible with ever smaller array line pitches, yet capable of impressing a sufficiently high voltage across a selected memory cell.
Such a forward set/reverse reset memory array requires voltages that may exceed the breakdown voltages (i.e., BVDSS) of the high voltage transistors that fit efficiently on the side of the memory array, and which are available for implementing such decoder circuits. Such a memory array also requires row and/or column decoders that have dual polarity outputs (i.e., active low outputs for one mode, and active high outputs for another mode).